ASIC design drill sergeant
Architecture
Choices that are made at the architectural level of an ASIC have far more reaching affects than choices made at any other level of the design, such as RTL or gate. That means these choices must be well thought out and modeled accurately. Otherwise, there’s the chance the design will not make its performance goals, or possibly even fail to match the design specification.
Sarge has been involved in many architectural decisions in the past, and knows what needs to be done to make sure the design will meet its goals. Making a model which can be used for both architectural exploration as well as verification environment development is something Sarge is especially skilled at doing.
One example of his architecture work is his performance analysis done on the L2 cache for the G4 PowerPC chip while working for Apple. He’s created models of a USB 2.0 hub, a networking memory block, an I2C master/slave, as well as many others.
Speak with Sarge today to find out how he can assist with your current architectural effort. Getting him involved at this level is the most cost effective engagement possible, and will reap huge benefits down the ilne on your ASIC design.
Sarge’s Invincible Consulting© 2008